The narrative around domestic motor driver chips has long been dominated by one term: Pin-to-Pin. Zhongke Micro’s AT8870 can replace TI’s DRV8870 pin for pin, “reducing costs by 10%~20%”; NOVOSENSE’s real-time control MCU hardware pin layout and software architecture are “highly compatible with international mainstream products,” “reducing customer migration costs and accelerating project switching.” This logic is clear and effective, but it defines a replaceable supplier, not the definer of a scenario solution.
When another group of products appeared in the industry, the competitive logic began to change. Fortior Technology’s FU75xx, released at the end of 2025, was described as “the industry’s first motor-drive dedicated MCU based on a 32-bit RISC-V dual-core architecture,” suitable for robot joints. Zhongke Semiconductor’s CT-Unite kit incorporates control algorithms into its self-developed RMCS V1.0 motion control platform, so OEMs do not need to build a control framework from scratch. In 2025, Yingfunaisi installed its self-developed high-side driver chips in 500,000 electric vehicles, “holding the top spot in a segmented track,” and advanced its H-bridge chips to whole-vehicle deployment at Dongfeng.
These moves no longer point to “making a chip that can be substituted,” but to using chip architecture to respond to a system-level requirement in scenarios not yet locked by standard products. One is substitution logic; the other is definition logic. The difference between them is not about the level of technical capability, but about how deeply chip vendors intervene in the discretion space of downstream system architecture—that is, scenario definition power.
Scenario definition power can be roughly divided into three observable boundaries: Level 1 is solution influence—chip vendors provide reference designs and supporting algorithms, but system specifications are led by downstream; Level 2 is architecture co-determination—downstream adjusts controller and even motor-body design constraints to adapt to the chip architecture; Level 3 is forming a de facto standard—multiple independent downstream solutions proactively adapt to this architectural paradigm. The core criterion is whether the chip adapts to system specifications predetermined by downstream, or whether downstream system forms adjust for the chip architecture. Currently, most domestic vendors remain at Level 2 co-determination and still have some distance to go before forming a cross-customer de facto standard.
Correspondingly, the observable returns are realized in layers: Level 1 influence only shows as customers preferentially adopting the original manufacturer’s reference solution, while selection still retains multi-supplier benchmarking; at Level 2 architecture co-determination, vendors can escape the Pin-to-Pin price-comparison framework, obtain a reasonable premium, raise customers’ migration costs when switching platforms, and participate in discussions of next-generation system specifications in advance; upon reaching Level 3 de facto standard, a third-party supporting ecosystem will spontaneously form, making the vendor a reference paradigm within the track. Such benefits do not take effect automatically, however. Definition power itself is only a positional advantage at the architecture level; whether it can ultimately be converted into commercial results still depends on scenario scale, engineering constraints, and cooperative relationships.
The following three cases correspond to three different paths of intervention.
Fortior FU75xx: When the Architecture Choice Itself Becomes the Scenario Definition
The core value of FU75xx does not lie in the choice of RISC-V—an open instruction set that any vendor can use to develop chips. The real design focus is that Fortior makes its second-generation ME2 motor hardware control engine and the RISC-V core into a heterogeneous dual-core design with clear division of responsibilities: ME2 serves as the hardware core, carrying dedicated, flexibly configurable control algorithm modules; the RISC-V core handles communications and interaction, application logic, and upper-layer scheduling, with the two cores running in parallel. In servo scenarios, this architecture can compress FOC computation to within 5μs, with current-loop bandwidth up to 3kHz, while the hardware modules natively integrate vibration suppression and torque compensation.
The rationality of this architecture is rooted in the specific scenario requirements of robot joints and industrial servo. A general-purpose motor drive MCU does not need to simultaneously handle both a nanosecond-level low-latency control loop and the compute overhead of complex encoders and industrial communication protocols; but robot joints have exactly this dual requirement: the control loop must be high-speed and stable, while also connecting to multiple types of encoders and industrial buses such as EtherCAT/CANFD/CANopen. The integration of rich interfaces such as BiSS-C and Tamagawa absolute encoders jointly shapes a “new” product category: it redefines the boundary of responsibility between hardware and software in joint servo scenarios.
Furthermore, Fortior’s involvement in the scenario goes beyond chips. Fortior and Sanhua Holding established a joint venture focused on coreless motor bodies, with Fortior holding 36% and Sanhua Holding in a controlling position. In other words, Fortior’s architecture definition was made in the process of advancing in parallel with actuator solutions: the physical constraints and control requirements of coreless motors and joint modules were fed back into the ME2 algorithm modules and interface configuration of FU75xx. The source of definition authority is not RISC-V itself, but the depth of the chip vendor’s involvement in downstream system solutions. Only when chip architecture and actuator architecture are discussed at the same table does “scenario definition” have substantive content, rather than being just a positioning slogan.
But there is a tension here that warrants continued questioning: Fortior is not the controlling party in the joint venture, and the final definition authority for joint modules lies on Sanhua’s side. To what extent the chip vendor’s involvement in the scenario can be translated into a voice at the architecture level, or whether it will mostly manifest as “adapting to existing solutions,” depends on the actual distribution of technical decision-making in the joint venture. FU75xx is a powerful starting point, but the sustained exercise of definition authority requires the chip vendor to repeatedly prove, in every subsequent scenario, that its judgment precedes the customer’s expression of requirements.
Zhongke CT-Unite: The Algorithm Is Not in the Customer’s Hands
Zhongke Semiconductor CT-2001B is a joint-oriented integrated drive-and-control chip, paired with the RMCS V1.0 motion control platform. It encapsulates a full set of control algorithms—including FOC, ADRC, MPC, trajectory planning, parameter identification, torque compensation, encoder calibration, compliant force control, and active vibration damping—within a self-developed platform. Equipment manufacturers do not need to build a control framework from scratch; they only need to complete parameter tuning through a visual interface or API.
In other words, control over the low-level control algorithms remains with the original manufacturer; what customers receive is a solidified and tuned control solution. Debugging according to the original manufacturer’s process essentially means following the original manufacturer’s control paradigm. According to information disclosed by the manufacturer, for joint solutions adapted to this platform, the prototype-to-mass-production cycle can be compressed to 45 days; currently, the solution has been deployed in projects with multiple leading customers.
But the “specialization” path inherently comes with the cost of ecosystem lock-in, and overseas major vendors have long set precedents: TI InstaSPIN hardwires core observer algorithms into the chip and pairs them with the dedicated MotorSuite calibration tool, so customers’ entire calibration and debugging workflow is highly dependent on the original vendor’s software stack. Heterogeneous cores, hardware control links, and proprietary algorithm frameworks customized for robot joints are themselves tightly coupled to a specific control paradigm. This can bring higher customer stickiness and pricing premium, but it also reduces the chip’s ability to be reused across scenarios. Once demand in the downstream track contracts or a leading customer’s project pivots, a highly customized architecture is hard to migrate quickly to other markets; the tuning experience and software code customers accumulate on this platform create two-way lock-in, which both raises barriers for external competitors and limits the freedom of subsequent chip architecture iteration. The premium brought by the right to define also comes at the cost of weaker generality and ecosystem lock-in.
Inverness: Using credibility in established categories to pave the way for emerging categories
Fengtao and Zhongke can be seen as competing for the right to define through architectural innovation in emerging incremental scenarios; Inverness takes a different and more robust path: first build supply-chain credibility recognized by automakers in mature established tracks, and when an adjacent track reaches a window for architectural reconstruction, migrate that credibility to the adjacent category and establish a voice in the new track.
In 2025, Inverness’s high-side driver chips were used in 500,000 new energy vehicles, “standing firmly at the top of the segment,” and its business has surged over the past three years. High-side drivers are basic actuator devices with a high degree of standardization in domain-control architectures, in a mature track with stable specifications. In this category, large-scale installation records and continuously validated automotive-grade reliability constitute important supply-chain credibility assets.
The value of this credibility shows when the opportunity window arrives. During domain-control architecture iteration, there is room to re-examine the supporting scheme, protection logic, and interface definitions for H-bridge drivers, and specifications are not yet fully fixed. Leveraging automaker trust, automotive-grade validation experience, and domain-control support collaboration accumulated from the high-side driver business, Inverness jointly developed the INB1060 H-bridge chip with Dongfeng, rather than entering directly with a Pin-to-Pin solution benchmarked against existing overseas devices.
Naxin Micro is the best reference sample: it has a larger automotive-grade shipment base covering more categories, and holds the full AEC-Q100 and ASIL-D automotive-grade qualifications. In mature tracks with already fixed specifications, such as automotive lighting and some general-purpose isolated drivers, it follows Pin-to-Pin compatible solutions and enters the supply chain as a replacement supplier; in window-period scenarios of E/E architecture transformation, such as next-generation electric drive platforms and automotive actuator MCU + driver subsystems, it chooses to deeply co-define chip specifications with Tier1s such as Lianhe Power, combining multiple discrete devices into a single integrated solution, with downstream adjusting controller hardware boundaries for this single-chip solution and entering a state of co-definition at the secondary architecture level. The same vendor, with the same supply-chain credibility asset, can choose replacement logic or definition logic in scenarios with different degrees of standardization.
This is the essence of this path: the reliability and trust accumulated in established tracks are a ticket with higher priority. Without this credibility, a vendor may still participate in architecture co-definition in new scenarios, but validation costs and customer concerns will be significantly higher; conversely, if the system specifications for an H-bridge have already been locked down by downstream, even with high automaker trust, customers will most likely still require the chip to follow established specifications and serve as a benchmarked replacement.
In short, credibility amplifies the probability of seizing definition opportunities, but the establishment of the right to define still depends on the same premise: the downstream system architecture is in a window period that has not yet been fixed, and downstream is willing to adjust design constraints for the new solution.
All three cases landed right in this window. The drive architecture for robot joints is still in its formative stage, and control algorithms have not yet settled on a unified platform paradigm. The category boundary between high-side drivers and H-bridges has not been fully solidified under domain-control architectures—definition power is exercised in these “unfixed” gaps. Moving from standardized device supply to system-level scenario architecture definition is also a long-running evolution trend in the global motor driver chip track.
But this does not mean the Pin-to-Pin logic is receding. Categories with already solidified specifications account for the majority; if customers change solutions, they have to go through validation again and redo certification, which, all things considered, is less attractive than direct price comparison—for such demand, replacement is the optimal solution. The layout of 纳芯微 mentioned above is also a microcosm of the current domestic motor driver chip industry—it is in a dual-track state rather than single-line evolution: some categories and vendors remain in the replacement logic, relying on supply chain efficiency and cost competition; others migrate toward definition logic, relying on intervention in scenario system architecture to gain pricing power and customer stickiness.
The same is true of leading international vendors: on the one hand, they continue to iterate standardized, pin-compatible general-purpose driver devices to meet the existing market’s demand for supply chain alternatives and rapid material replacement; on the other hand, targeting high-value iterative tracks such as industrial servos and automotive domain control, they continue to launch dedicated SoC products integrating hardware control engines, power supplies, and pre-drivers. Overseas vendors’ layouts are also responding to downstream high-end systems’ inherent demand for low latency and high integration.
Domestic vendors’ differentiation opportunity lies more in relying on China’s complete industrial chain clusters for motors, modules, and complete vehicles, which gives them shorter cross-link collaboration cycles, but they also need to face the engineering, organizational, and ecosystem constraints common to this route. The condition for divergence between the two tracks is not the broad label of “technical capability,” but the degree of scenario standardization, the concentration of downstream system vendors, and whether chip vendors have the organizational capability to define architecture together with customers.
峰岹’s FU75xx and 中科’s CT-Unite prove that definition logic is feasible both technically and commercially, but they each also expose the boundaries of definition power: 峰岹 needs to handle the allocation of technical voice in a joint venture relationship, while 中科 needs to answer how much autonomy customers retain after platform binding. 英弗耐思 demonstrates another more robust but longer path—first accumulate sufficient credibility in existing categories, then migrate to adjacent incremental categories. The common point of the three paths is that chip vendors no longer wait for customers to propose specifications, but proactively enter the discretionary space of system architecture. This is exactly the substance that distinguishes “scenario definition power” from “Pin-to-Pin replacement,” and it is also the core variable in the next stage of competition for domestic motor driver chips.